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RISC-V-32bit-RTL-Physical-Design

mounikag425vlsi-boop

RISC-V 32-bit RTL Physical Design project using OpenLane, OpenROAD, Yosys, OpenSTA, Magic, Docker, and Sky130 PDK.

B

integrated-vlsi-physical-design-Sure-ProEd

Bhanu-Sharma466

Physical Design (RTL-to-GDSII) implementation of a digital ASIC block completed under the SURE ProEd Integrated VLSI Internship Program. Covers complete flow execution using OpenLane and SkyWater 130nm PDK, including RTL synthesis, floorplanning, placement, CTS, routing, PPA analysis, and DRC/LVS signoff verification.

B

Single_Stage_Differential_OpAmp

Bharadwaj300

CMOS single-stage differential op-amp featuring an active load architecture. Validated through AC magnitude/phase plots and transient response simulations to determine open-loop gain and bandwidth.

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VLSI_PD

shamstanveerg425integratedvlsi

Final report for the Physical Design (VLSI) project at IERY (SURE Trust), mentored by Veeramani Sir (Synopsys). Covers the OpenLane RTL-to-GDSII flow on SkyWater SKY130: Linux and OpenLane setup, spm analysis, 4-bit and 32-bit up/down counters, and the PicoRV32 RISC-V core, with timing, power, area, IR drop and routing analysis.

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PicoRV32-Physical-Design-

arjun111-p

PicoRV32 RISC-V physical design project completed during the Sure ProEd VLSI internship (G3-25-VLSI). Covers OpenLane, OpenROAD, SKY130A, synthesis, STA, floorplanning, placement, PDN, CTS, routing and timing analysis.

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Physica-Design-VLSI-Openlane

viveksai848

Completed a VLSI Physical Design project as part of my SURE Trust internship, gaining hands-on exposure to the ASIC backend flow, including floorplanning, placement, CTS, routing, and timing analysis. The project strengthened my understanding of physical design methodologies and key design parameters such as timing, area, power, and congestion.

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Physica-Design-VLSI

viveksai848

Completed a VLSI Physical Design project as part of my SURE Trust internship, gaining hands-on exposure to the ASIC backend flow, including floorplanning, placement, CTS, routing, and timing analysis. The project strengthened my understanding of physical design methodologies and key design parameters such as timing, area, power, and congestion.

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5-stage-RISC-V

guru753

Designed a 32-bit RV32I RISC-V processor in Verilog using the 5-stage pipeline (IF, ID, EX, MEM, WB). Supported R-type, I-type, load/store, branch, jump and U-type instructions. Implemented PC, register file, ALU, control unit, forwarding, hazard detection, load-use stalls, and branch/jump flushing for reliable pipeline execution flow. verified

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vlsi-physical-design-openlane

SanjanaSuresh05

Hands-on VLSI physical design work using OpenLane and OpenROAD, covering RTL-to-GDSII implementation, STA, timing closure, power and area analysis, routing, IR-drop analysis, and TCL-based automation.

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physical-design-1

jeevang425VLSI

RTL-to-GDSII physical design and verification of the PicoRV32 32-bit RV32I RISC-V processor using OpenLane, with hands-on exposure to synthesis, floorplanning, placement, CTS, routing, STA, timing analysis, DRC, PDN, IR-drop analysis, TCL scripting, and physical-design report interpretation.

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vlsi-physical-design-openlane

avinashbankur

Hands-on VLSI physical design work using OpenLane and OpenROAD, covering RTL-to-GDSII implementation, STA, timing closure, power and area analysis, routing, IR-drop analysis, and TCL-based automation.

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Physical-Design-flow-for-RISC-V-picorv32-

mandalaganesh633-ai

Implemented the complete Physical Design flow of a 32-bit RISC-V processor using OpenLane. Gained hands-on experience with synthesis, floorplanning, power planning, placement, CTS, routing, and signoff. Worked with LEF, DEF, Liberty, and SDC files while analyzing timing, area, utilization, and power reports using OpenROAD.

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Vending-Machine-Controller-Design

peramamatha

This project implements a configurable Vending Machine Controller in Verilog RTL based on an industry-style IP specification. It supports dynamic item configuration, asynchronous currency and item inputs, and cycle-accurate dispense control.

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Design-Verification-using-UVM-Methodology-Vending-Machine-Controller-IP

Srikumar281

This project focuses on the design verification of a Vending Machine Controller IP using the Universal Verification Methodology (UVM). The primary objective is to verify the functional correctness, robustness, and scalability of a configurable vending machine controller designed as a reusable digital IP for SoC integration.

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ANUSHA-G1-25-VLSI

Anusha7893

Designed and verified a Vending Machine Controller using system verilog HDL , UVM. Performed many test scenarios.

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Integrated-VLSI-designing

Sasikala108

This project involves the functional verification of a Vending Machine Controller IP using SystemVerilog and UVM. A reusable UVM testbench was developed to verify APB-based configuration, item selection, currency handling, dispense logic, and change calculation across different operating modes using directed and constrained-random testing.

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vending_machine_controller_using_Verilog_HDL

UshaButi

This project implements a **vending machine controller using Verilog HDL** based on a **Finite State Machine (FSM)**. It handles item selection, currency validation, balance calculation, and product dispensing in a synchronous digital design.

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Vending-Machine

Marthalaharipriya123

This project involves designing a Vending Machine Controller using Verilog HDL. It implements FSM-based control, currency handling, and configurable item management. The design follows a modular RTL approach and is verified through simulation.

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vending_machine_controller_vlsi_project

sumitarohit

UVM-based Vending Machine Controller project developed during my 6-month Integrated VLSI Internship at Sure ProEd (Sure Trust). Includes verification environment, and simulation results.

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PALLA_PAVAN_KUMAR_DFT_PROJECT

PAVAN-KUMAR-PALLA

This project contains implementation and theoretical knowledge necessary for efficient post-manufacturing testing of integrated circuits, primarily through the use of scan chains. Scan chains connect flip-flops into a shift register, enhancing controllability and observability of internal nodes for defect detection.

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DFT-Project

Tharunkrishna123

**Scan Insertion** is a Design for Testability (DFT) technique where flip-flops are converted into **scan flip-flops (SFFs)** and linked into **scan chains**. This allows test vectors to be **shifted in and out**, giving controllability and observability of internal states.

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DFT-PROJECT-SURE_TRUST

Vijjvijay

This project focuses on implementation of a design with clock rules, DRC fixing, PLL integration, and scan insertion — gaining practical insights into real-world ASIC design flows.

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Vending-Machine-Controller

JnaneswarChandaka

This project is a Verilog RTL-based implementation of a configurable vending machine controller. It simulates a real vending system with support for dynamic item setup, asynchronous user input, and real-time dispensing logic. The design is modular, parameterized, and optimized for both configurability and fast operation.

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project__design-of-single-stage-differential-amplifier

Mani654

In this project, I designed and simulated a single-stage differential amplifier using 90nm CMOS technology in Cadence Virtuoso, an industry-standard tool for analog and mixed-signal (AMS) design.

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Vending-Machine-Design

Susrutha144

This project implements a complete Vending Machine Controller in Verilog HDL, built with a modular architecture, support for multiple clock domains, and APB-based configuration. It operates in both configuration and operational modes, enabling real-time item selection, purchase, and dispensing based on valid currency inputs.

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Vending-machine-design

N-KEERTHI-2004

This project implements a Vending Machine Controller in Verilog, designed with APB interface support for configuration and monitoring. It integrates currency handling, item memory management, and control logic into a modular, scalable architecture.

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VENDING_MACHINE_CONTROLLER

MaramVenkataLakshmiPrasanna

his repository hosts the Vending Machine Controller (VMC) RTL design and its functional verification environment. The RTL, written in Verilog, supports up to 1024 programmable items with dynamic configuration via an APB interface.

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RTL-TO-GDSII-FLOW-OF-RISC_V-32-BIT-PROCESSOR

Preethigrace-7

Build up myself with extendable knowledge from Fundamentals of VLSI to Chip Tapeout. Worked on RISCV 32bit processor from RTL to GDSII flow with specified Industry standard constraints using Open source tool Openlane.

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Scan-insertion-with-DRC-and-coverage-analysis

Chanduu001

This project showcases the end-to-end design, modification, and verification of a digital circuit, emphasizing Design Rule Check (DRC) compliance and industry-standard practices. The work integrates both physical and logical design aspects, ensuring a reliable and testable implementation.

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Vending-Machine-Controller-Sure-Trust

sharan0908

This repository contains the RTL verification environment and testbench for a Vending Machine Controller design. The project focuses on verifying the functional correctness of the controller using UVM (Universal Verification Methodology).

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SURETrust

navyachiluka

"VLSI Integrated" is a 6-month online internship that provides training across all domains of VLSI. In the final phase, we choose one specialization and complete a project in that area. I have opted for RTL Design and worked on a Vending Machine Controller. This repository contains all the modules related to the Vending Machine Controller project.

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differential_amplifier

sunny0-vlsi

The project involves the design and analysis of a differential amplifier, a core analog circuit used to amplify the difference between two input signals while rejecting common-mode noise. It was implemented and simulated using Cadence Virtuoso, focusing on parameters like gain, CMRR, and biasing stability.

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SURE-Trust-Vending_Machine

prasannakumar1824

This is the design of Vending Machine ,which includes Reset Mode, configuration mode, operation mode. This is designed meeting with the real time vending machine specifications.

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KATA_SUBRAMANYAM_G3_INTEGRATED_VLSI

Subbu-kata

This project is a fully functional Vending Machine Controller designed using Verilog HDL, featuring modular design, multi-clock domain handling, and APB-based configuration. The system supports both configuration and operation modes, allowing real-time selection, purchase, and dispensing of items based on valid currency input.

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vending_machine

Krishnasa1

This project implements a Verilog-based Vending Machine Controller with support for APB configuration, item dispensing, and currency validation. It features FSM control, clock domain synchronization, and is fully synthesizable for FPGA applications.

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vending-machine

pasambaladitya123

This project, developed under SURE Trust, presents a scalable Verilog-based vending machine controller using FSM and modular RTL design. It handles asynchronous inputs, supports APB configuration, and enables real-time dispensing to enhance performance and flexibility.

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Vending-machine

Parinika-E

A Vending Machine Controller is a digital system that manages the operation of a vending machine,including item selection,dispensing and change/refund handling.it ensures correct item delivery based on user input and available balance using sequential logic

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Vending-Machine

SOWJANYA-MADANA

A Verilog-based RTL design of a configurable vending machine controller with APB configuration, asynchronous input handling, and real-time item dispensing.

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Vending-Machine

mramyasri777

This repository features a Verilog-based vending machine controller IP core, supporting multi-clock domain operation, inventory management, and currency denominations. Built with the APB protocol for efficient configuration, it offers smart change calculation and robust error handling. Developed in the SURE ProEd internship training with experts.

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Vending-Machine

Preven-K

This repository features a Verilog-based vending machine controller IP core, supporting multi-clock domain operation, inventory management, and currency denominations. Built with the APB protocol for efficient configuration, it offers smart change calculation and robust error handling. Developed in the SURE ProEd internship training with experts.